Designers of digital integrated circuits (ICs) use various software tools to design an IC. The design engineer typically writes code in a Hardware Design Language (HDL), also known as a Register Transfer Language (RTL). The IC designer then runs a simulator which tests the design using the HDL code as input. After fixing any problems found in the code by the simulation process, the HDL code is then used as input by a synthesizer. The synthesizer translates the HDL code into a physical representation of an IC, which can then be produced as a physical IC in the form of an Field Programmable Gate Array (FPGA), Application-Specific Integrated Circuit (ASIC), or custom silicon IC.
During the simulation process, a verification engineer instruments the HDL code with assertions to verify that the HDL code is an accurate implementation of the intended design. An assertion is a statement which expresses how a particular design feature should or should not behave. For example, the code for a particular logic block may assume that only one of two input signals is active at any one time. As another example, a logic block may assume that an input will never be larger than a certain maximum value. As yet another example, a logic block may assume that a request signal will remain asserted until after an acknowledge signal is asserted. Each of these assumptions made by the designer can be expressed as assertion.
After creating these assertions, the verification engineer typically inserts the assertions into appropriate areas of the HDL source file. However, this manual insertion method is not desirable because both the design engineer and the verification engineer need to update the same file. Source-code control tools can be used to prevent the two engineers from updating the file at the same time. Using such systems, one engineer “checks out” the file, makes his changes, and checks it back in.
In addition, the type of assertion whether using PSL or SVA (System Verilog Assertion) can be determined at merge time. This allows the IC designer to choose the “best” type of assertion to use for his/her purposes. The current fad may be to use OVL (Open Verification Library) but within two years it will be SVA which has more powerful capabilities. In any case, the specific identifier remains with the RTL code to increase the documentation purpose also.
However, the process of inserting assertions manually is still problematic, since while the verification engineer is creating the assertions and instrumenting the HDL code with them, the HDL source file is unavailable to the design engineer. By not inserting verbose assertion information, the RTL code remains cleaner and is not obfuscated by other types of coding. Therefore, a better process of integrating assertions with HDL source code is needed.